(1) Field of the Invention
The present invention relates to a data packing circuit, which is used in a variable length coder, for receiving code words including variable length codes, and successively packing the codes having variable lengths with no gaps into successive units of bits having a predetermined length, for example, successive bytes of data.
In data transmission systems wherein variable length coding is used, original data words are successively encoded into code words including variable length codes in the sender side, and the variable length codes (effective portions of the code words) having variable lengths are successively packed in byte or word lengths with no gaps for transmission through a transmission line with a high efficiency. In the receiver side, the above packed variable length codes, when received, are respectively unpacked into the code words having a byte length.
Generally, it is required to reduce the delay time in transmitting data in data transmission systems, and therefore, the reduction of the delay time is also required in the above operation of packing code words.
(2) Description of the Related Art
FIG. 1 shows a construction of a data packing circuit in a variable length coder in the prior art. In FIG. 1, reference numeral 60 denotes a variable length coding circuit, 61 denotes a clock generator, 62 denotes a parallel to serial conversion circuit, and 63 denotes a memory circuit. The variable length coding circuit 60 successively encodes original data words into code words including variable length codes, and outputs a code word in a parallel form together with information on the code length when receiving a READY signal. The code word output from the variable length coding circuit 60, is loaded in parallel in the shift register 62. The clock generator 61 generates a number of clock pulses, where the number is equal to the above code length, and the clock pulses are supplied to the parallel to serial conversion circuit 62 for providing timing for serially reading out each bit of the variable length code included in the above loaded code word. The code which is serially output from the parallel to serial conversion circuit 62 is written in the memory circuit 63. The above clock pulses are also supplied to the memory circuit 63 for providing timing for serially writing the above code in the memory circuit 63. As the number of the clock pulses is equal to the code length, only an effective portion of each code word, i.e., the variable length code is written in the memory circuit 63. The memory circuit 63 functions as a buffer memory, and the above serially output bits of the codes are successively written therein with no gaps, i.e., the codes are successively packed therein with no gaps. The packed codes are serially output from the memory circuit 63 at the transmission rate of the transmission line. When all bits of the codes loaded in the parallel to serial conversion circuit 62 is read out, the clock generator 61 outputs a READY signal to the variable length coding circuit 60 to load a next code word in the parallel to serial conversion circuit 62.
However, in the construction of FIG. 1, it takes much time to carry out the above packing operation mainly due to the use of the parallel to serial conversion of code words. The delay time in the above operation is an obstacle for a high-speed data transmission. To solve this problem, the frequency of the internal clock must be increased, but the increase in the frequency of the internal clock imposes severe requirements regarding the design of the circuitry for its high-speed operation. For example, high-speed and precise circuit elements must be used for the construction of the circuitry, and the use of the high-speed circuit elements has a tendency to increase power consumption. Therefore, the cost of constructing and using the circuitry is increased.
The Japanese Unexamined Patent Publication No. 61-265974 discloses a variable length coding apparatus wherein a ROM (read only memory) and a RAM (random access memory) are provided, the ROM memorizes all possible bit patterns of codes in all the possible bit-shifted forms, and the RAM holds codes packed with no gaps. When each code is packed in the RAM, the position to which the first bit of the following code is to be located for packing the following code with no gaps from the last bit of the above packed code, is memorized in a register, and the address for outputting a shifted bit pattern from the ROM is supplied to the ROM based on the following code and the above memorized position of the first bit of the following code. A logical sum of the output of the ROM and the last word in the RAM including the above memorized position is obtained in an OR gate set, and the output of the OR gate set is held in the RAM.
However, in the above construction, mainly due to the use of the ROM and the RAM, the scale of the circuitry and the cost of constructing the circuitry are large, and the delay time in packing data is not short.